The present invention relates to a semiconductor memory device including a dynamic memory element.
A memory operation of a dynamic memory element composed of one capacitor and one transistor is performed by, as known well, supplying the capacitor with electric charges and thus holding bit data in this state. The electric charges, i.e., the data, supplied to the capacitor are dissipated with a passage of time due to a leak current from insulating films constituting the transistor and the capacitor. For this reason, the semiconductor memory device including the dynamic memory element is so constructed that the capacitor is automatically recharged (refresh operation) at an interval of a fixed time by providing a refresh timer circuit. The dissipation of the data is thus prevented.
The prior art will hereinafter be described with reference to FIGS., 12 and 13. FIG. 12 is a circuit diagram illustrating a unit of the dynamic memory element. FIG. 13 is a characteristic diagram showing a temperature characteristic of an electric charge holding time of the conventional dynamic memory element versus a refresh cycle.
FIG. 12 illustrates a dynamic memory element 1 formed on a silicon semiconductor substrate. This dynamic memory element 1 comprises a transistor 4, having a gate connected to a switching line 2 and a source connected to a data line 3, for performing a switching operation. The dynamic memory element 1 also comprises a capacitor 5 connected between a drain of this transistor 4 and the ground. The numeral 6 designates a gate insulting film of the transistor 4, and the numeral 7 represents an electrode-to-electrode insulating film interposed between electrodes of the capacitor 5. Both of these insulating films are formed of silicon oxide (SiO.sub.2).
A plurality of dynamic memory elements 1 are provided on a semiconductor substrate together with other unillustrated circuit elements and wiring, thus constituting a semiconductor memory device.
In such a dynamic memory element 1, the electric charges supplied to the capacitor 5 flow in the form of a leak current. Then, the leak current increases with a rise in temperature, and, therefore, it follows that an electric charge holding time X of the dynamic memory element 1, as indicated by the solid line in FIG. 13, changes to increase when at a low temperature but decrease when at a high temperature. From the above-mentioned, a refresh operation of the dynamic memory element 1 is carried out in a predetermined electric charge holding time and is assured within a predetermined temperature range.
On the other hand, the refresh timer circuit for performing the refresh operation of the dynamic memory element 1 via the data line 3 is typically constructed of a transistor, and the refresh cycle receives almost no influence by the temperature.
For this reason, a refresh cycle C0 of the thus constructed refresh timer circuit is set based on the shortest electric charge holding time with a maximum temperature value TMAX falling within the temperature range defined as an operation assurance range. More specifically, for example, if the operation assurance range is from 0.degree. C. to 80.degree. C., the refresh cycle C0 is set to a fixed time Xc0 shorter than an electric charge holding time X80 when the maximum temperature value TMAX=80.degree. C. Note that the refresh cycle C0 is indicated by the solid line in FIG. 9, and there exists a difference on the order of substantially two digits between the electric charge holding time X80 when the maximum temperature value TMAX=80.degree. C. and an electric charge holding time X00 when the minimum temperature value TMIN=0.degree. C.
However, the operation of the semiconductor memory device having the above dynamic memory elements 1 and the refresh timer circuit is often effected within a range of, e.g., 20.degree. C. through 40.degree. C. that is a narrower temperature range than the operation assurance range, the electric charge holding time at the operation-often-conducted temperatures 20.degree. C. through 40.degree. C. is as long as X20 through X40. Nevertheless, it follows that the refresh operation is carried out with the initially-set short time Xc0 serving as the refresh cycle C0.
Performing such a refresh operation entails an increase in cumulative quantity of the electric current required for refreshing because of effecting the refreshing at a more increased frequency than needed. This therefore requires a refresh power supply having a large current capacity, and, when a battery is used, a large-sized battery having the large capacity has to be employed, or alternatively the battery has to be charged or replaced at an increased frequency. Note that when constructing the semiconductor memory device with the operating temperature range made narrower in conformity with individual operating conditions, the generalization of the semiconductor memory device for use is restricted.
As stated above, according to the prior art, the refresh operation of the dynamic memory element is assured in the temperature range broader than an actual operation range, and, hence, the large-capacity poser supply is needed. Besides, the semiconductor memory device involves the use of the battery as a power supply is brought into such a situation that the battery is replaced at the increased frequency.